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FPGA Technology Architect

Location: San Jose, CA, United States 
Req ID: 9100000306


Western Digital®
We deliver the possibilities of data.  YOU define what’s possible.

Do you have a passion working on leading edge technology? Are you passionate about working closely with next generation enterprise SSDs? Are you a fast learner and enjoy synthesizing knowledge in to practice? Western Digital is a leader in the design of world class enterprise class SSD products. We are looking for a strong FPGA Design Engineer to work on next generation enterprise SSD FPGA Development Platforms. The candidate must be a highly motivated self-starter who will thrive in this dynamic, cutting-edge environment. A fundamental part of our strategy is having desirable and powerful Development Platform that enable Engineering teams to deliver products at fast pace. Creating these platforms involves a close partnership between Hardware team, Firmware engineers, ASIC designers, and Program team. We are currently building the next generation Platform and we need you!

You are responsible for providing technical expertise in all domains for FPGA system. You will be developing FPGA reusable custom IPs to streamline FPGA porting, work with FPGA RTL team and implementation engineers to provide support for FPGA architecture, IP, primitive, clocking, reset and other FPGA components. Create/use high speed interface IPs using LVDS signaling, GTx IPs, understanding target FPGA architecture limitations and identifying best use of available resources. Working with FPGA vendors to resolve design and tool issues at rapid pace. Be the go-to engineer for FPGA


  • Must have strong knowledge of FPGA internal architecture and different hard block IPs available in target FPGA
  • Should be able to grasp components in RTL design and be able to analyze FPGA utilization to find any synthesis/ mapping issues
  • Design and implement FPGA clocking and Reset structure for the system
  • Understand and exercise advanced features in FPGA and FPGA implementation tools
  • Customize C2C Ips for design needs with location and timing constraints
  • Assign physical design constraints and floor plan the design
    Perform Static Timing Analysis and optimize critical paths to achieve maximum possible system clocks for the system
  • Communicate benefits of available FPGA internal resources to FPGA design team and how it can be used to simplify FPGA implementations for both area and speed
  • Define optimized, streamlined FPGA build flow to achieve timing met images in best possible time
  • Work with hardware design team in defining FPGA IO usage for future platforms
  • Motivated and self-driven. A Team player is a must
  • Proficiency with Microsoft Office applications such as Word, Excel, and PowerPoint, Visio is desired
  • #LI-SS1



  • Minimum 12 years’ experience in FPGA designs

  • Proven track record of successful FPGA design implementations

  • Experience with RTL Simulation tools, Synplify Premier, Identify debugger,

  • Xilinx Vivado, Xilinx ILA, ARM ICE debuggers

  • Experience understanding hardware schematic

  • Bachelor's/Master's degree in Electrical Engineering or related technical degree is required



Western Digital Corporation is the world’s largest data storage company with a leading portfolio of HGST, SanDisk, G-Technology and WD brands covering flash and disk-based solutions.  Deployed by the largest and most prominent organizations worldwide, Western Digital solutions are everywhere, touching lives and enabling great value from the data they possess. 


Western Digital is an equal opportunity employer. We are committed to providing equal employment opportunity for all applicants and employees. Western Digital does not unlawfully discriminate and complies with the laws and regulations set forth in the following EEO Is The Law poster: Equal Employment Opportunity Is The Law.


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