Looking for ASIC Verification Engineer, responsible for:
Development of ASIC verification and Validation plans
Development of UVM and C test cases for ASIC verification and validation to achieve comprehensive coverage
Working with ASIC design and architecture teams to understand functionality of logic blocks of SSD controller
Comprehending "big picture" at the ASIC architectural and system level as well as executing at the detail block level.
- Master degree in Electrical Engineering or Computer Science.
- 8+ years of applicable experience.
- Knowledge of HDL and experience in behavioral and RTL coding, Verilog preferred.
- Knowledge of ARM AMBA Bus protocols
- Knowledge of C and SystemVerilog.
- Knowledge of UVM verification methodology and testbench architecture
- Experience in C code development for System validation.
- Familiar with scripting language like Perl/Python