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Technologist, Packaging Engineering

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Location: Kfar Saba, IL, Israel 
Req ID: JR-9999035427



  • Packaging Technologist manages Package Development activities for Memory controllers (ASIC) design in cooperation with SanDisk worldwide ASIC teams (Israel, India, USA) and multiple Product Development groups within the company.
  • Packaging Technologist manages an entire cycle of ASIC package development: Analyzes of System and ASIC Product requirements, Assembly Technology benchmarking and selection, multidisciplinary Feasibility study, Cost effectiveness studies, Package design with Thermo-Mech Finite Element validations, Signal and Power Integrity analysis, Bill of Materials. Prepares and updates various packaging specifications.
  • Coordinates with factories worldwide on the Eng Samples deliveries, Package Qualification plan, Production low/ high volume introduction of new packages and/ or new assembly processes. Manages assembly yield improvement and package cost reduction programs.  Represents Package Engineering Org in cross-functional teams and ensures that packages are characterized, qualified and transferred in production in a timely manner while meeting all electrical, performance, reliability and quality requirements.

  • MS / PhD degree in Mechanical, Material Engineering or Electrical Engineering (VLSI) or equivalent with 10-12 years of relevant work experience in microelectronic assembly industry.
  • Solid knowledge and experience of Package development flow, advance microelectronic Packaging technologies, Assembly and Semiconductor FAB processing, tooling and materials.
  • Knowledge of Controller (ASIC) architecture design principles and Phys design flow.
  • Knowledge of Package Signal and Power integrity basics- impedance and matching, high frequency signal and propagation, cross-talk, coupling, material property influence, Package RLC, etc.
  • Knowledge of EMI, HFSS, HSPICE models -advantage.
  • Hands-on experience with oscilloscopes, network analyzers and spectrum analyzers- advantage.
  • Knowledge of Package and Board Level Reliability Qualification, various Industrial standards and requirements (JEDEC; MIL, else).
  • Proven practical skill in DOE planning and statistical Analyzes (JMP), Package failure analysis methodology and techniques. Practical skill in AutoCAD, Cadence APD, Finite Element Analysis (ANSYS).
  • Ability to daily multi-tasking in different projects, manage and meet tight deadlines of packaging deliverables as a part of multidisciplinary team as well as excellent communication and interpersonal skills required.