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Senior Engineer, Packaging Engineering

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Location: Taichung, TXG, Taiwan 
Req ID: JR-0000036540


Optimize die bonding pad and substrate(BGA, LGA, SIP)/ PCB layouts for possible design simplification and cost reduction of Multi-Chip stack die packages and memory card PCB. Explore routing and placement changes that could lower the substrate complexity and cost. Provide substrate layout feasibility and documentation for laminate package designs. Perform Design Library maintenance and bonding diagram generation. Perform cost/performance trade–off analysis of various packages either in production or under development. Interface seamlessly with product managers, substrate designers, manufacturing and assembly engineering and layout groups at the assembly subcontractors. Work closely with various manufacturing and packaging groups at various Western Digital  locations for new product development and substrate / PCB design improvement. Work with assembly houses and substrate / PCB vendors on design review and design rule maintenance.