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Senior Manager, ASIC Development Engineering

Location: Bangalore, KA, India 
Req ID: JR-0000036899

Description

  • Job Description

    List of responsibilities includes but not limited to the following tasks.

    • Prepare and implement a robust end to end / comprehensive RTL verification test plan for IP verification and FPGA rapid prototyping.
    • Develop any needed verification /regression enabling automation tools / methods / flows as needed.
    • Be familiar with SerDEs architecture implementation and prepare and implement IP/sub system level test bench along with relevant test cases (directed / randomized)with appropriate assertions and drive to meet set coverage goals.
    • Be familiar with RAL standards for register validation.
    • Be familiar with NLP flows for UPF based low power verification and GLS flows.
    • Be familiar with verification of industry standard micro controllers like Xtensa u controllers which are used for high speed channel receiver adaptation / calibration.
    • Set clear expectations of coverage metrics vis-a-vis code coverage / functional / feature driven coverage and drive to achieve the same.
    • Possess sharp test content creation, debugging skills and file for bugs and close on them in a timely fashion.
    • Work with cross functional teams on enabling FPGA prototypes for emulation and or post silicon debug.

    Qualifications:

    • BE/ME/MTech/MS with 10~12 years of SerDes RTL verification experience.
    • Experience in IP level and sub-system level verification on protocols like PCI-E Gen1/2/3/4, USB 3.0/31, SATA 1/2/3 is a must.
    • Must have experience in creating and executing a robust verification test plan leading a small team of verification engineers.
    • Must have relevant experience in enabling and verifying controller interoperability testing at sub system level.
    • Relevant experience in verification of protocols like UFS Gear 1/2/3/4 is a strong plus.
    • Must be well versed in using advanced verification methodologies like UVM/OVM/VMM/System Verilog, constrained random stimulus generation, assertion based verification and functional coverage techniques.
    • Must be well versed in RAL standards, NLP/GLS verification flows.
    • Familiarity with RTL design aspects like Physical Coding sub layer, Physical media access blocks in SV or VHDL is a strong plus.
    • Basic familiarity with high level advanced receiver adaptation techniques which may include fsm or ucontroller based firm- ware driven equalization is a strong plus.
    • Basic Knowledge of real value modelling of channel impulse response for receiver adaptation / equalization verification is a strong plus.