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Principal Engineer

Location: Bangalore, KA, India 
Req ID: JR-0000036354


6-8 year ACT 

Strong digital fundamentals: latches, Flops, Combination logic 

Good in depth knowledge of transistor level circuits

Strong timing understanding from digital: setup/hold, constraints etc

Strongly focused on the technical aspects of design closure, checks etc

Good knowledge of HSpice and Finesim tools


Should have worked on architectures: Custom datapath, DLL, Clocking schemes 

Strong understanding of DRAM/DDR interface timing 

Mentor juniors and technical lead the team for the projects 

Should be able to take up people reporting 

Have good knowledge of DDR systems and timing



Drive new architecture schemes to improve datapath timing

Able to lead Custom data path design and timing 

Come up with new architecture improvements and proposals 

Mentor juniors to ramp them and be productive