ESSENTIAL DUTIES AND RESPONSIBILITIES:
- Perform logic design and verification of memory products, including micro-architecture
- Register Transaction Leve (RTL) design implementation, test case generation, modeling and debugging
- Provide constraints to logic synthesis team to translate design into gate level and fix timing issues before silicon tapeout
- Develop firmware for memory chip operations
- Validate and debug design features on silicon
- Work with manufacturing and test teams to ensure product delivery
· Require a minimum of BS in EE or CS/CE with 3 years of experience or MS in EE or CS/CE with 2 years of experience.