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Staff Engineer, PHY Digital Design

Location: Bangalore, KA, India 
Req ID: JR-0000037645


The ideal individual must have:Contribute to the development and verification of advanced SERDES PCS/PMA logic, including CDR, Channel/equalization Adaptation, clock domains crossing, calibration logic, auto-negotiation, BER eye monitor, etcDevelop micro-architecture and test-chip/test-system specificationsDevelop Verilog test benches, diagnostics, and product test flow procedures.Interface with customers and assist in integrating the Serdes IPParticipate in all test chip and bring up activitiesHelp improve RTL design and verification methodologyRequired Experience:Bachelor/Master/Phd in Electronics/Electrical Engineering with 4+ years of experience in SerDes PMAb and PCS RTL Development design.Expertise in SERDES protocols and PCS/PMA architecture such as PCIe,, USB, SATA, UFS etcExperience in PHY-level protocol test suite development and integration with link layer controllersExperience in high speed FPGA RTL porting, IO mapping, synthesis, timing closureVerilog/System Verilog, functional verification skillsKnowledgeable in advanced RTL digital design methodologyWorking experience with Lint, CDC, Synthesis/P&R/STA, CTS, Xilinx FPGA compiler toolsExcellent team player and clear communicatorAbility to operate lab equipment like Oscilloscope etc