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Senior Verification Engineer

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Location: Bangalore, KA, India 
Req ID: JR-0000037820


Experience:               3-6 years Years of experience in the following areas:- Functional Verification:•Assertion Based Verification (ABV) setup•System Verilog Assertion Hands-on (a must)•SVA based Verification plan development•Exposure in Verilog/System Verilog/UVM Test bench application•Exposure in Formal based Verification•Verification closure using coverage metrics•RTL & Gate Level Simulations•Proficiency in Verilog, System Verilog & Assertions•Verification Automation using scripts  like Perl,shell,tcl/tk•Exposure to Analog verification will additional plus point-Digital design Concepts                -  CMOS VLSI, Digital Circuits                -  Knowledge on Memory (preferred)                  (SRAM/DRAM/ROM/Flash) Circuits/Logic                - Expertise in following CAD Tools                                - NCSIM, IMC, IEV, Verdi, Jasper, VS Formal                                - Cadence Schematic and layout environment