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Principal Engineer

Location: Bangalore, KA, India 
Req ID: JR-0000038382

Description

  • The key functions and responsibilities are the following:

    ·         Define and Implement the ASIC/SoC verification environment.

    ·         Develop block and system-level test benches and verification environments using Verilog/SystemVerilog and C.

    ·         Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.

    ·         Mentor verification team and provide technical support for verification activities

    ·         Support the development of  verification test plans, test suites and verification activities

     

    Essential Technical Expertise:

    ·         Experience in ASIC/SoC verification activities and should have participated in successful completion of at least one ASIC/SoC project from Specifications to Silicon.

    ·         Must have good understanding of embedded processor based SoC architecture and must have completed verification of two or more embedded processor based SoC.

    ·         Must have expertise in on ASIC verification methodologies and ASIC design flow.

    ·         Must have good experience in setting up and debugging functional and gate level simulation have multiple processors (co-simulation).

    ·         Must have good experience in developing BFM and functional models in Verilog/System Verilog/UVM.

    ·         Proven experience of the design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation.

    ·         Must have complete experience on developing verification environment and test cases from planning stage to tape-out signoff.

    ·         Must have actively conducted functional / coverage review and bug management schemes.

    ·         Protocol Knowledge on PCIe, UFS2, SATA and USB2.0/3.0 is added advantage.

    ·         Self-motivation, flexibility, with strong inter-personal skills.

    ·         Good communication skills, oral and written skills.

     

    Required Experience:

    ·         7+  years’ experience in Frontend ASIC verification flow.

    ·         Should have 1-2 years’ experience as a team leader.

    ·         Should have experience in leading verification team  from verification paling to through tape-out signoff and post silicon verification experience is appreciated.

    ·         Should have expertise in Verilog and SV

    ·         Should have experience in a multi-site environment, interacting with teams in other sites.

    ·         Should possess good managerial skills and communication skills