Education requirements/Preference: Bachelor or Master Degree in Electrical/Electronics Engineering
The ideal individual must have:
- Proven ability to achieve results in a fast moving, dynamic environment.
- Self-motivated and self-directed, however, must have demonstrated ability to work well with people.
- A proven desire to work as a team member, both on the same team and outside of the team.
- The ability to troubleshoot and analyze complex SoC System problems.
- Ability to multi-task and meet deadlines.
- 7-12 years’ experience in Frontend ASIC design flow.
- Should have experience in implementing IP design from specification through Silicon debug/characterization.
- Should have experience with bandwidth analysis and architectural exploration of Multi Core SoC Design
- Should have good understanding of Firmware & Hardware interactions and trade-offs
- Should have complete understanding of issues for RTL to GDSII flow of Modern Multi Core SoC Designs
- Should have understanding of challenges of FPGA emulation of design.
- Should have experience in a multi-site environment, interacting with teams in other sites.
- Should possess good interpersonal and Mentoring Skills
Tasks to be performed & areas of responsibility
- Will be responsible for SoC/IP Architectural exploration and feasibility analysis
- Take Critical Role in SoC and IP Design Activities
- Complement the US team in development of ASIC architecture
- Should provide leadership in terms of end-to-end technical management
- Responsible for building team and developing processes
- Should bid for new projects/activities
- Mentoring and supporting Junior engineers