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Staff Engineer, ASIC Development Engineering

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Location: Bangalore, KA, India 
Req ID: JR-0000038267


  • Job description

    MSIP Senior Engineer would be responsible for full custom layout of high performance mixed signal IP’s for controller ASIC. Responsible for work independently on block level and chip level Analog layout design, coordinating with the circuit designer & layout lead of various analog/IO blocks like – High Speed/High Performance IOs, ESD protection, Linear Voltage Regulators, Temperature Sensors, AFE for high speed/high drive interfaces, data convertors etc.

    Candidate would be expected to work closely with the inter-continental teams including participation in internal meetings and review sessions.

    Candidate will be responsible for the project development cycle by innovative design solutions/methodologies.

    The ideal individual must have:

    • Proven ability to achieve results in a fast moving, dynamic environment.
    • Self-motivated and self-directed, however, must have demonstrated ability to work well with people.
    • A proven desire to work as a team member, both on the same team and outside of the team.
    • The ability to troubleshoot and analyze complex problems.
    • Ability to multi-task and meet deadlines.

    Required Experience:

    Must have

    • Bachelor/Master in Electronics/Electrical Engineering with 3+ years of experience in High Speed IOs & Analog IPs full custom layout.
    • Candidate should work independently on block level and chip level Analog layout design, coordinating with the circuit designer & the layout lead
    • Candidate should have 3+ years of hands-on experience in Analog or RF layout.
    • Custom layout experience in high frequency circuits such as VCOs, PLL, LDO, High Speed Phy etc.
    • Full Understanding of IC fabrication and reliability issues
    • Full familiarity with Cadence-Virtuoso, PVS, ASSURA and Calibre tools
    • Familiarity with failure mechanisms, reliability issues and solutions  - ESD, Latch-up guidelines, testing and debugging
    • Experience in Signal Integrity simulations, SSN simulations, eye diagrams etc
    • Familiarity with timing budget, different components of the budget and their measurement for some signaling standards
    • Good documentation, communication and presentation skills