The Tools team is developing a wide range of FPGA solution for post silicon validation for memory devices across Western Digital.
The team is looking for a talented, energetic verification engineer with ~5 years of experience in UVM environment both IP and system level.
Qualifications & Experience:
• At least 5 years of experience in Asic or FPGA verification.
• Knowledge in System Verilog.
• Ability to plan and write verification components BFM’s/Monitors/Checkers etc'.
• Knowledge in advanced verification infrastructures such as UVM, VMM, etc. – a must!!
• Excellent knowledge of one or more scripting languages (TCL, Perl, Python)
• Experience as RTL Designer – an advantage
• Deep knowledge of the following tools:
NCSim – advantage