In this position, the individual will assist block level STA teams with timing closure. The individual will be responsible for RTL synthesis and development-debug of interface and core side timing constraints and clock tree analysis. He / She will also drive IP integration strategies that ensure quality ASICs and avoid schedule surprises.The individual must have a strong desire to learn and must be a go getter. Basic Understanding of static timing analysis flow, tape-out process and experience in PERL/TCL/Shell scripting is a must. Expertise in PrimeTime and PrimeTime-SI is desired. Ability to work with minimal supervision and drive to exceed expectations is a must. Good verbal and written communication skills are required.