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Staff Engineer

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Location: Bangalore, KA, India 
Req ID: JR-0000038898


  • Responsibilities include:

    • Developing Memory Emulation/FPGA Models using Verilog RTL coding for Emulation Platform
    • Contributing FPGA synthesis, partitioning and routing tools for Memory Models
    • Develops hardware and software collaterals and integrates it with the emulation/FPGA platform.
    • Tests and debugs the Memory Model deployed in the emulation/FPGA platform
    • Developing new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post Silicon functional validation.
    • Verifying the developed emulation model with Pre-Si Verification Methodologies (using System Verilog based UVM Methodology) & Post Si tools.
    • Exposure with programing and scripting languages.
    • Involve in Design integration, logic synthesize, and design optimization for area.
  • Additional Job Description
    • Digital Logic Design using Verilog HDL
    • FPGA and Emulation model development using Verilog HDL
    • Logic synthesis & principles with power/timing estimation
    • System validation using in-circuit emulation development and FPGA fast prototyping.
    • Familiar with pre-Silicon prototyping tools, flows and methodologies.
    • Real hands on experience of mapping complex design into Emulation platforms like Palladium or Veloce or FPGA Proto typing.
    • Good understanding of Logic Design & Architecture
    • Exposure with EDA Tools like Cadence NCSIM, Verdi, SVN, AccuRev
    • Effective communication skills and a good team player
    • Strong Problem Solving & Communication skill is a must

    This position involves in-depth understanding of the Memory Design and Logic Design. Design flow from RTL to emulation and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, models development for emulation and verifying emulation models with pre-si tools and post Si tools.