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Principal Engineer

Location: Bangalore, KA, India 
Req ID: JR-0000038930

Description

    • Proficiency in digital design concepts.
    • Experience in Custom circuit design. Some basic analog knowledge would be helpful.
    • Good understanding of RTL. Knowledge of Verilog language is required.
    • Understanding of Synthesis/PnR flow is a bonus.
    • Knowledge of spice simulations tools and Cadence environment.
    • Layout understanding.
    • Excellent oral and written communication skills.

    The selected candidate would be required to do the following:

    • Verify logic and timing of Datapath circuits between IO and Memory ARRAY.
    • Design custom circuits to meet specific project requirements.
    • Spec to RTL.
    • Circuit and layout modelling for spice simulations.
    • Layout checks.
    • Mentor NCGs.