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Technician 2, Mask Design Engineering

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Location: Milpitas, CA, United States 
Req ID: JR-0000038795


Western Digital®


We deliver the possibilities of data.  YOU define what’s possible.


The Memory Technology Group is at the core of the Legacy SanDisk Engineering Organization which Western Digital owns. We are building a cutting edge 3D memory in our multiple billion dollars Fab. Our memory provides performance, power, and endurance at a lower cost but on quality. The Memory Technology organization is a strategic entity for the company, and we are growing. Our group functions as a start-up within WDC, and offers a creative, fast paced, entrepreneurial work environment where you’ll be at the center of WDC innovation.


We are looking for an experienced Designers to lead and deliver projects for our Memory Design team as well as talented and highly motivation junior engineers. This is a great opportunity for a results-oriented, entrepreneurial individual who knows how to work with non-volatile memory world-class engineers and who has a great track record for delivering innovative results.


You will need to think creatively about the memory as we do take pride in our craftsmanship.  We do work together with all engineering teams to identify and execute on the most disciplined way. Your success will be measured by your ability to build great designs that deliver innovation that unlock revenue opportunities for the company.

Join the Memory Technology Design Team and become a leader of this highly motivated, cooperative and focused team!




  • The competent individual should have basic knowledge of semiconductor electronic devices, layout mask drawings and related EDA tools used in drawing and verifying.
  • Engineer should have good understanding and experience of standard cells and Macro layout design and verification.
  • Exposure and hands on experience of small to mid-sized analog and digital block layouts like differential amplifiers, OPAMPS, Current source, Power system sub-blocks.
  • Experience with memory layout.
  • Complete understanding of GDR layout design rules, devices, physical verification – DRC, LVS.
  • Good understanding of layout parasitic, ESD and latch-up.
  • Capable on DRC/LVS debugging.

·        Understanding layout basics/concepts

·        Standard cell layout knowledge

·        Exposure and hands on to block level layout design

·        Basic understanding of memory layout

·        Basic understanding of analog layout concepts – Matching, shielding, Symmetry

·        Basic understanding of ESD, Reliability and DFM concepts

·        Handling of digital blocks using custom router

·        Experience of EDA tools: Cadence Virtuoso Layout Editor, Synopsys Hercules, Mentor Graphics

·        Good knowledge on Unix/Linux, vi editor, xcel, ppt…etc.

  • Good communication skill, detail oriented, and great team player.
  • Years of experience required è 0 – 2 years
  • Education requirement è AA/BA




Western Digital Corporation is the world’s largest data storage company with a leading portfolio of HGST, SanDisk, G-Technology and WD brands covering flash and disk-based solutions.  Deployed by the largest and most prominent organizations worldwide, Western Digital solutions are everywhere, touching lives and enabling great value from the data they possess. 


Western Digital is an equal opportunity employer. We are committed to providing equal employment opportunity for all applicants and employees. Western Digital does not unlawfully discriminate and complies with the laws and regulations set forth in the following EEO Is The Law poster: Equal Employment Opportunity Is The Law.


Western Digital participates in the E-Verify program in the US. For more information click here. Este empleador participa in E-Verify.