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Senior Engineer, ASIC Development Engineering

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Location: Bangalore, KA, India 
Req ID: JR-0000040850


Sr. Engineer

Req ID: JR-0000040850

Western Digital®
We deliver the possibilities of data. YOU define what’s possible.
Job Description:

Responsibilities will include complete ownership of sub chip PnR environment, clock tree design and driving Place-And-Route flow for full chip convergence and timing closer.

Job Qualifications:
The individual must have a strong desire to learn and must be a go getter. 
Having exposure to Physical Verification flow for DRC and LVS closure for blocks is preferred. 
Ability to work with minimal supervision and drive to exceed expectations is a must.  
Good verbal and written communication skills are required.
This position requires a Master’s Degree in Electrical Engineering or Computer Science with a minimum of 8 to 12 years of hands on experience in sub chip / full chip Place-And-Route flow with emphasis on 16 nm and 7nm designs. 
Proficiency in ICC / ICC II and experience in PERL/TCL/Shell scripting is a must.


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